1. Field of the Invention
The present invention relates to forming conductive patterns on a semiconductor substrate and more specifically to a selective deposition technique connecting various conducting layers during the formation of an integrated circuit.
2. Prior Art
In the manufacture of multiple conductive layer semiconductor devices, such as a double-metal integrated circuit chip, a variety of processes for forming conductive patterns to interconnect various conducting layers of such a device is well-known in the technology. These conductive patterns are commonly formed by a subtractive process, wherein a deposition of a conducting layer over a silicon wafer surface is followed by photolithographic and etching processes for patterning. Evaporation and sputtering techniques are two well-known methods of depositing the conductive layer. The etching process is generally accomplished by wet chemicals or by ionized gas, such as plasma. Normally, a conducting layer is deposited over a silicon wafer with an insulating oxide layer, and then the photolithographic and etching techniques are used to remove the conducting material from unmasked areas such that the desired conducting pattern remains over the underlying layer.
An entirely different approach is to use an additive process wherein the conductive material is deposited selectively only over the area where the conducting layer is to be formed. By selectively adding the conductive material only over the desired area where the conducting layer is to be formed, the etching step can be avoided during such a process.
An example of such an additive process is a lift-off process in which a mask of the conductive pattern is first formed on the underlying material, and then the conductive material is deposited over the entire wafer. The unwanted conducting material is then removed by "lifting-off" by dissolving the photoresist material in a suitable solvent. In this technique, the conducting material is deposited over the mask, whereas with the subtractive process the conductive layer is formed under the photoresistive mask. This additive process requires a deposition step as well as a masking step, but removes the necessity of an etching step. However, because of the necessity of providing a complete conducting layer above the mask for the lift-off technique, it is still not a true additive process.
In the fabrication of high-density integrated circuits, a significant problem is in attempting to obtain planarization of the various layers to obtain a smooth topology. Planarization is necessary to reduce formation of voids, cracks and other well-known undesirable features. However, where interconnections are required between the various conducting layers, openings (vias, holes, windows) are cut into the various insulating layers separating the conducting layers, so that interconnections can be formed between the conducting layers. Because a conductive material needs to fill these various vertical openings, planarization is difficult to achieve and significant problems are encountered in attempting to planarize this layer by utilizing conventional etching methods.
A recent technique has been to utilize a truly additive process of electroless plating to fill these various openings. One such technique is taught in "The Characterization of Via-Filling Technology With Electroless Plating Method", reference 1 cited below, wherein electroless nickel plating using palladium activation is used to fill 2.0 um or larger via holes to achieve substantially planarized upper surface above the via. Although various electrochemical techniques for electroless deposition of metals have been known in the prior art and are described in the prior art references cited below, such use of electroless plating to deposit metals to form substantially planarized semiconductive layers have not been practiced until recently.
The present invention describes a novel metallization process which is both additive and selective to provide conducting layers, as well as an interconnection between layers of a multiple conducting layer semiconductor device for the manufacture of LSI and VLSI circuits.
References:
(1) Yusuke Harada et al., "The Characterization of Via-Filling Technology with Electroless Plating Method", Journal of the Electrochemical Society, Volume 133, pages 2428-2429, November 1986.
(2) M. Paunovic, "Electrochemical Aspects of Electroless Deposition of Metals", Plating, Volume 55, pages 1161-1167, November 1968 (Prior Art).
(3) M. Paunovic, "An Electrochemical Control System for Electoless Copper Bath", Journal of the Electrochemical Society, Volume 127, No. 2, pages 365-369, February 1980 (Prior Art).
(4) L.A. D'Asaro et al., "Electroless Gold Plating on III-V Compound Crystals", Journal of the Electrochemical Society, Volume 127, pages 1935-1940, September 1980 (Prior Art).
(5) Milan Paunovic, "Electrochemical Aspects of Electroless Nickel Deposition", Plating and Surface Finishing, Volume 70, pages 62-66, February 1983 (Prior Art).
(6) U.S. Pat. No. 4,122,215 (Vratny) (Prior Art).
(7) U.S. Pat. No. 4,154,877 (Vratny) (Prior Art).
(8) M. Paunovic, "Activation for Electrochemical Metal Deposition on Nonconductors", Abstract 21, The Electrochemical Society Extended Abstracts, Volume 86-1, page 31, May 1986 (Prior Art).
(9) Milan Paunovic, "Photochemical Selective Activation for Electroless Metal Deposition on Nonconductors", Journal of the Electrochemical Society, Volume 127, pages 441c-447c, September 1980 (Prior Art).
(10) Fred Pearlstein, "Electroless Plating", in Modern Electroplating, Edited by F.A. Lowenheim, John Wiley & Sons, Inc., pages 710-747, 1974 (Prior Art).
(11) S.B. Felch and J.S. Sonico, "A Wet Etch for Polysilicon with High Selectivity to Photoresist", Solid State Technology, page 70, September 1986 (Prior Art).